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Agilent HDMP-3268 3.2 Gbit/sec 68x68 Crosspoint Switch
Data Sheet
Features * Supports data rates up to 3.2 Gbit/sec on each channel * Fully differential high-speed signal path for highest signal integrity * Implemented as 68 independent 68-input multiplexers * Supports broadcast/multicast modes. Inputs can be connected to multiple outputs * Provides two independent switch matrix configuration register sets * Low jitter, low crosstalk * Individually programmable highspeed output signal amplitude to optimize drive of various PCB and backplane distances * Individually programmable input equalization for better signal integrity * Unused input and output channels can be powered off to reduce power consumption * Broadcast programming mode to rapidly configure the default switch settings * SSTL_2 and LVTTL compatible inputs and outputs on the programming bus and the control signals * Single supply voltage of 2.5 V * Low power 13.5 W maximum * Packaged in a 400-pin High Performance Ball Grid Array (HPBGA) * Implemented in a high performance BiCMOS process Applications * Optical cross connect switches * Optical add-drop multiplexers * Telecom switches * Other optical (OEO) switch fabrics * Backplane interconnect switch fabrics
Description The HDMP-3268 is a 68x68 digital crosspoint switch with data handling capacities of up to 3.2 Gbit/sec on each channel. The non-blocking switch uses 68 fully independent multiplexers to allow each output port to be independently programmed to be connected to any input port. All data channels are designed with a fully differential architecture to insure data integrity and resistance to noise and crosstalk. The part is designed in a reliable BiCMOS process, operates off of a single 2.5 V supply and is packaged in a 400 pin HPBGA. Data comes in to each of the 68 ports as a DC balanced differential signal (DIN[0:67]). Each input port then presents the data to the input of a multiplexer, which routes the signal to the selected output port (DOUT[0:67]). Input and output ports are required to be AC-coupled unless connected to either this or another HDMP-3268. The crosspoint switch multiplexers are controlled by
68 address registers (one for each multiplexer). The address registers are programmed through the program and control pins. The high-speed input buffer contains input equalization to improve signal integrity over copper traces. The equalization may be modified on an individual port basis through use of the program and control pins (DATA[6:0], CH[6:0], WSTB, CNTL, CS and RW). The crosspoint switch address and control register configuration may be read back from the switch through use of the RW and CNTL inputs. The DC levels of the high speed outputs are consistent with the input levels of the high speed inputs. Therefore, the outputs of the HDMP-3268 can be connected to inputs of the HDMP-3268 without blocking capacitors as long as the supply voltages for the two parts are identical.
Block Description Figure 1 gives an overall block diagram for the HDMP-3268. The operation of HDMP-3268 is discussed below.
DIN[0:67]+ DIN[0:67]-
HIGH SPEED INPUT
SWITCH MATRIX
HIGH SPEED OUTPUT
DOUT[0:67]+ DOUT[0:67]-
ON/OFF, EQUALIZATION
ON/OFF, AMPLITUDE INPUT CHANNEL ADDRESS0 REGISTERS ADDRESS1 REGISTERS USE SET
WSTB
CONTROL REGISTERS
CONTROL LOGIC
DATA MUX
CNTL
CH[6:0] TERM
CS
RW
DATA [6:0]
Figure 1. Block diagram for the HDMP-3268.
HS_OUT
VCC_DOUT 50 50 AC DOUT+ DOUT- Zo = 50 Zo = 50 DIN+ DIN- *0.1 F *AC COUPLING CAPACITORS ARE NOT REQUIRED IF THE OUTPUT OF THE HDMP-3268 IS DRIVING THE INPUT OF THIS OR ANOTHER HDMP-3268. VCC
HS_IN
~ 0.7 V ~
50
50
GND
GND
Figure 2. High-speed output and input simplified circuit schematics.
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High-Speed Inputs and Outputs Figure 2 shows simplified circuit diagrams for the HDMP-3268's high speed input and output cells. A typical connection between the output and input cells is also shown. The output cell is designed to drive 50 transmission lines and to be terminated at the destination end in 50 . When the output is intended to connect to the input of another HDMP-3268 as in a CLOS architecture, no AC coupling capacitors are required. The output amplitude of the HDMP3268 is programmable in three levels from approximately 500 mV to 1.0 V peak-to-peak differential. In addition, the output driver and its associated multiplexer can be turned off to save power if an output is not used. The HDMP-3268 high speed input cell provides on-chip termination resistors of 50 from each input to an on-chip bias voltage generator which sets the input common mode voltage at approximately 0.7 V below the positive supply. When the input is intended to be DC coupled, as in the case of the input being connected to the output of another HDMP-3268, the
common mode bias voltage is disconnected from the termination resistors, and the two 50 resistors form a 100 differential termination. DC coupling is the default setting for the HDMP-3268. The input cell has levels of input equalization which can be programmed through the digital control interface. The AC termination voltage also can be enabled through a control register. Unused input cells can be disabled to save power. Figure 3 shows a typical transfer characteristic of the high-speed input for the different input equalization settings. The correct equalization setting depends upon the actual PCB environment in which the HDMP-3268 resides. The recommended procedure to set the input equalization setting is to characterize the HDMP-3268 on the PCB and to adjust the equalization setting to give minimum jitter at the output of the HDMP-3268. The correct equalization settings should be stored and loaded into the HDMP-3268 upon power-up. The AC characteristics of the high speed input, high speed output, and multiplexer block are specified in Table 8, AC Electrical Specifications.
Digital Interface The HDMP-3268 has a parallel bidirectional digital interface for configuring the switch matrix and for controlling the various functions such as input equalization, output amplitude, and power on/off. All of the registers can be read back to check valid programming. There are 204 7-bit registers organized into three sets of 68 registers each. One set is used to control power on/off, equalization, etc. The other two sets are used to configure the switch matrix. The individual registers are accessed using an address/data scheme. The particular register address is placed on the CH[6:0] lines, and the register data is placed on the DATA[6:0] lines, either by the controller in write mode (RW=0), or by the HDMP-3268 in read mode (RW=1). Data is latched into the internal registers on the rising edge of WSTB. The control registers are accessed when the CNTL signal is high. Otherwise, the address registers are accessed. Figure 4 and Table 1 show the register read and write timing diagram and specifications. See the switch matrix configuration section for more details. A chip select signal allows
HIGH SPEED INPUT AC TRANSFER CHARACTERISTIC BOOST 3 dB
TYPICAL PERFORMANCE OF HIGH SPEED INPUT CELL WITH DIFFERENT EQUALIZATION SETTINGS EQUALIZATION SETTING 000 001 010 GAINDC (dB) 16.0 11.4 12.9 12.9 12.9 12.9 10.5 9.8 BOOST (dB) 0 3.7 4.8 5.4 5.8 6.1 6.5 7.3 Fpeak (GHz) N/A 3.4 2.7 2.3 2.0 1.8 1.8 1.8 F3dB (GHz) 7.9 10.7 10.2 10.0 9.8 9.8 10.6 11.2
GAINDC
GAIN
011 100 101 110 111 Fpeak F3dB FREQUENCY
THIS DATA IS FOR ILLUSTRATIVE PURPOSES ONLY.
Figure 3. Typical high-speed input equalization curve.
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multiple HDMP-3268s to reside on the same address and data buses. When CS is high, the HDMP-3268 does not accept data, and the HDMP-3268's data outputs are tri-stated. In
broadcast write mode, (CH[6:0] set to `1111111'), all registers of the selected set (control or address) receive the same data value. This feature simplifies chip configuration upon power-up. By
default, all registers are programmed to 0 at power-up provided VCC comes up at the same time or after VDD.
WRITE MODE READ MODE WSTB tpw
CS
PW CH[6:0] SET CNTL DATA[6:0] tWHiZ tDsetup tCsetup tCHsetup tChold tCHhold tDhold tperiod
tcs
tDaccess
Figure 4. Timing diagram for accessing HDMP-3268 registers.
Table 1. HDMP-3268 Interface Timing Requirements TA = 0C to TC = 85C, VCC = VDD = VCC_DOUT = 2.35 V to 2.65 V Symbol tperiod tpw trise/fall tDsetup tDhold tCHsetup tCHhold tCsetup tChold tcs tDaccess tWHiZ Parameter Write Strobe Period Write Strobe Pulse Width Write Strobe Rise and Fall Times Data Setup Time Data Hold Time Channel Setup Time Channel Hold Time Control Setup Time Control Hold Time Chip Select to Data Out Data Access Time Write Assert to High Z Time Units ns ns ns ns ns ns ns ns ns ns ns ns 2 0.5 8 1 4 -0.7 3 -1.2 5 10 3 7.4 13 4 1 0 Min. 15.2 3 0.6* tperiod 2 Typ. Max.
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Control Register The control register is used to program the input AC or DC coupling, input equalization, output amplitude and power
on/off settings of each input and output of the crosspoint switch. To access the control register the control signal CNTL must be high. Table 2 gives the specific
definition of each bit in the control register. Upon power-up, all bits of the control register are set to 0.
Table 2. HDMP-3268 Control Register Definition Bit(s) 6:5 Name Output On/Off & Amplitude[1] Value 00 01 10 11 000 111 0 1 0 1 Definition Output stage disabled (power off) Typical Vop[1] = 550 mV Typical Vop[1] = 800 mV Typical Vop[1] = 1050 mV Input equalization disabled Maximum input equalization Input stage disabled (power off) Input stage active (power on) DC input coupling AC input coupling
4:2 1 0
Equalization Amplitude Input On/Off AC/DC
Note: 1. Output Peak-to-Peak Differential Voltage, Vop, is specified as DOUT+ minus DOUT-. This measurement is made using a repeating 1010 pattern with a 100 termination resistor across the DOUT+ and DOUT- outputs. The swing doubles if there is no termination resistor.
Switch Matrix Configuration The address registers are used to program the connectivity of the switch matrix. The address registers are accessed when the CNTL input is low. There are two independent banks of 68 address registers to allow one bank to be programmed while the other bank
is controlling the switch matrix if desired. There is one Address0 register and one Address1 register per output channel. The address register selects the input to be connected to its output. Connecting a particular input to a particular output is done by setting CH[6:0] to the desired
output channel. DATA[6:0] holds the channel number of the desired input channel. Table 3 summarizes the behavior of the USE and SET bits. See Figure 4 for the timing diagram for SET, and Figure 5 for the timing diagram for USE.
Table 3. USE/SET Truth Table Use Set Address Register Use 0 0 1 1 0 1 0 1 Using Address0 Registers for switch control, Reading/Writing Address0 Registers Using Address0 Registers for switch control, Reading/Writing Address1 Registers Using Address1 Registers for switch control, Reading/Writing Address0 Registers Using Address1 Registers for switch control, Reading/Writing Address1 Registers
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USE
tDvalid
DOUT
tDinv
Figure 5. USE bit data valid/invalid timing diagram.
Table 4. USE Bit Timing TA = 0C to TC = 85C, VCC = VDD = VCC_DOUT = 2.35 V to 2.65 V Symbol tDvalid tDinv Parameter USE bit set to valid DOUT USE bit set to DOUT invalid Unit ns ns Min. 6 Typ. Max. 40
Digital Interface I/O Figure 6 shows simplified circuit diagrams of the digital input and output cells. The digital input cell is applicable to all data and control inputs of the HDMP-3268. The digital output cell used for the HDMP-3268's digital I/Os are designed to be compatible with either an SSTL_2 interface or with an LVTTL interface. The digital input cell has the option of providing an on-chip 50 termination resistor. The 50 termination is connected to the digital input when the TERM pin is high. When the HDMP-3268 is used with an SSTL_2 interface, the VREF output of the controlling chip should be connected to the VREFI pin on the HDMP-
3268. This gives the best noise margin performance since the VREF output signal of the controlling chip should be centered with respect to its output swing. Alternatively, for best performance, the HDMP-3268's VREFO output, which provides an output voltage of approximately one half of the supply, should be connected to the VREFI pin of the controlling chip. A 0.1 F bypass capacitor should also be connected at the VREFI pin. For an LVTTL interface, the HDMP-3268 provides a reference voltage of nominally 1.4 V on the VREF14 pin. When the HDMP3268 is used with a 3.3 V LVTTL system, its VREF14 pin should be
connected to its VREFI pin. The nominal output impedance for the digital output is 25 . Therefore, when connecting the HDMP-3268 unterminated for a distributed point-to-point topology, a 25 resistor should be added in series with the data I/O lines to match 50 traces on the PC board. For lumped circuit connections the 25 series resistor is not necessary. The HDMP-3268 has termination amplifiers built in for distributed multichip connections where the SSTL_2 I/Os need to be terminated. Note that a terminated connection consumes significant power, so terminations
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DIGITAL OUTPUT
VDD VDD
DIGITAL INPUT
I/O 25 NOMINAL OUTPUT IMPEDANCE
IN TERM VREFI x1 50
GND
GND
Figure 6. Digital I/O simplified circuit schematics.
CONTROLLER VREF0 0.1 F
HDMP-3268 VREF1
CONTROLLER
HDMP-3268 VREF1 VREF14 0.1 F
VREF1 0.1 F 25
50 DRIVING IMPEDANCE
VREF0
25 DATA I/O
25 DRIVING IMPEDANCE 50 DRIVING IMPEDANCE
DATA I/O
DATA I/O
DATA I/O 50 TRANSMISSION LINE
50 TRANSMISSION LINE
25 DRIVING IMPEDANCE
TERM
TERM
A) UNTERMINATED SSTL_2 CONNECTION
B) UNTERMINATED LVTTL CONNECTION
Figure 7. Unterminated digital I/O connections.
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should only be used if necessary. When TERM is pulled high to VDD all low speed digital inputs and I/Os except TERM itself are terminated. Pins affected are
WSTB, CH[6:0], CS, RW, DATA[6:0], CNTL, USE and SET. Since the transmission line is terminated at both ends, the driving impedance is 25 .
HDMP-3268s connected in the middle of the transmission line do not need to be terminated. Figure 8 shows a typical connection.
CONTROLLER VREF0 0.1 F
HDMP-3268 VREF1 0.1 F VREF0 0.1 F
HDMP-3268 VREF1 VREF0
VREF1
25 DRIVING IMPEDANCE INTERNALLY TERMINATED TO VREFI THROUGH 50
DATA I/O 50 TRANSMISSION LINE
DATA I/O
25 DRIVING IMPEDANCE
DATA I/O 50 TRANSMISSION LINE VDD TERM
25 DRIVING IMPEDANCE
TERM
TERMINATED SSTL_2 CONNECTION
Figure 8. Terminated SSTL_2 connection.
Table 5. HDMP-3268 Absolute Maximum Ratings TA = 25C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to the device. Symbol VDD VCC VCC_DOUT VIN VINHS Tj Tstg ESD Parameter Logic Supply Voltage Switch Array Power Supply High Speed Output Supply Input Voltage for WSTB, CH[6:0], CS, RW, DATA[6:0], CNTL High Speed Input Voltage for DIN[0:67]+ and DIN[0:67]Junction Temperature Storage Temperature ESD Rating (HBM) Units V V V V V
oC oC
Min. -0.5 -0.5 -0.5 -0.5 -0.5 0 -55
Max. 3.6 V 3.6 V 3.6 V VDD+1.25 V VCC+0.5 V[1] +125 +125 2
kV
Note: 1. VIN must remain less than or equal to the absolute maximum supply voltage of 3.6 V.
Table 6. HDMP-3268 Recommended Operating Conditions Symbol Parameter VDD VCC VCC_DOUT Ta Tc 8 Logic Supply Voltage Switch Array Power Supply High Speed Output Supply Ambient Temperature Case Temperature
Units V V V
oC oC
Min. 2.35 2.35 2.35 0
Typ. 2.5 2.5 2.5 25
Max. 2.65 2.65 2.65 85
Table 7. HDMP-3268 DC Electrical Specifications TA = 0C to Tc=+85oC, VCC = VDD = VCC_DOUT =2.35 V to 2.65 V Symbol VDD VCC VCC_DOUT Pd[2] Pd1[3] VOH_DU VOL_DU VOH_DT VOL_DT VIH_D (LVTTL) VIL_D (LVTTL) VIH_AC (SSTL_2) VIL_AC (SSTL_2) VIH_DC (SSTL_2) VIL_DC (SSTL_2) I IH_DU I IL_DU IIH_DT I IL_DT VREF14 VREFI VREFO Parameter Logic Supply Voltage Switch Array Power Supply High Speed Output Supply Power Dissipation [TERM = 0] Power Dissipation [TERM = 1] Digital Interface Unterminated Output High Voltage, IOH = -400 A Digital Interface Unterminated Output Low Voltage Level, IOL = 1 mA Digital Interface Terminated Output High Voltage Digital Interface Terminated Output Low Voltage Level Digital Interface Input High Voltage Level, guaranteed high signal, VREFI tied to VREF14 Digital Interface Input Low Voltage Level, guaranteed low signal, VREFI tied to VREF14 Digital Interface Input AC High Voltage Level, guaranteed high signal, VREFI = 1.15 V to 1.35 V Digital Interface Input AC Low Voltage Level, guaranteed low signal, VREFI = 1.15 V to 1.35 V Digital Interface Input DC High Voltage Level, guaranteed high signal, VREFI = 1.15 V to 1.35 V Digital Interface Input DC Low Voltage Level, guaranteed low signal, VREFI = 1.15 V to 1.35 V Digital Interface Unterminated Input High Current, VIN = 2.4 V, VCC=2.5 V Digital Interface Unterminated Input Low Current, VIN = 0.4 V, VCC=2.5 V Digital Interface Terminated Input High Current, VIN = 2.4 V, VCC=2.5 V Digital Interface Terminated Input Low Current, VIN = 0.4 V, VCC=2.5 V LVTTL Reference Output, TA = 25C SSTL_2 Reference Input, TA = 25C SSTL_2 Reference Output, TA = 25C Units V V V W W V V V V V 2.2 0 VREFO + 0.38 -0.3 2 Min. 2.35 2.35 2.35 Typ. 2.5 2.5 2.5 Max. 2.65 2.65 2.65 13.5 15.5 VDD 0.6 VDD+ 0.3 VREFO0.38
V V V V V A A mA mA V V V 1.15 1.15 VREFI+ 0.35 -0.3 VREFI+ 0.18 -0.3 -15 -15 -12.5 12.5 1.4 1.25 1.25
0.8 VDDQ+ 0.3[1] VREFI0.35 VDDQ+ 0.3[1] VREFI0.18 15 15
1.35 1.35
Notes: 1. VDDQ refers to the SSTL_2 power supply of the driving device. 2. Power Dissipation measurement was taken with a toggling pattern of 50 MHz applied to the high-speed input channels at 50% duty cycle. All inputs and outputs are turned on. 3. Power Dissipation measurement was taken with Input logic `0' applied to all control pins with a toggling pattern of 50 MHz applied to the highspeed input channels at 50% duty cycle. All inputs and outputs are turned on.
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Table 7.1. HDMP-3268 DC Electrical Specifications for Individual Power Supply Current TA = 25C , VCC = VDD = VCC_DOUT = 2.5 V Symbol Icc[4] Icc_dout[4] Idd (TERM=0)[4] Idd (TERM=1)[5] Units A A A A min_amp[1] (Typ) 1.5 1.5 0.0025 0.3 mid_amp[2] (Typ) 1.5 1.9 0.0025 0.3 max_amp[3] (Typ) 1.5 2.3 0.0025 0.3
Notes: 1. Current drawn from power supply, minimum output amplitude (mode 01). 2. Current drawn from power supply, mid output amplitude (mode 10). 3. Current drawn from power supply, maximum output amplitude (mode 11). 4. Current measurement was taken with a toggling pattern at 50 MHz is applied into the high-speed input channels at 50% duty cycle. All inputs and outputs are turned on. 5. Current measurement was taken with input logic '0` applied to all control pins and a toggling pattern at 50 MHz is applied into the high-speed input channels at 50% duty cycle. All inputs and outputs are turned on.
Table 7.2. HDMP-3268 DC Electrical Specifications for Current Drawn for Individual Input/Output Channel Turned on/off TA = 25C , VCC = VDD = VCC_DOUT = 2.5 V Symbol Din_ICC[1,2] Dout_ICC[1,3] Dout_ICC_DOUT[1,3] Parameters Current drawn when 1 input is turned on Current drawn for power supply VCC when 1 output is turned on Current drawn for power supply VCC_DOUT when 1 output is turned on Units mA mA mA Typical 16.0 7.4 34.0
Notes: 1. Current measurement was carried out using a toggling pattern at maximum amplitude with 50% duty cycle 2. For input channels, the number of input channels turned on/off affects only the power supply current for VCC. 3. For output channels, the number of output channels turned on/off affects only the power supply currents for VCC and VCC_DOUT.
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Table 8. HDMP-3268 AC Electrical Specifications TA = 0C to TC = +85C, VCC = VDD = VCC_DOUT = 2.35 V to 2.65 V Symbol trd, DOUT tfd, DOUT VIP, DIN VOP, DOUT01[1] VOP, DOUT10[1] VOP, DOUT11[1] tProp tskew part RJ (Single)[3] Parameter DOUT Differential Rise Time DOUT Differential Fall Time DIN Input Peak-To-Peak Differential Voltage DOUT Output Pk-Pk Diff. Voltage at minimum amplitude setting (Amplitude code=01) with 100 Ohm differential termination DOUT Output Pk-Pk Diff. Voltage at mid-range amplitude setting (Amplitude code=10) with 100 Ohm differential termination DOUT Output Pk-Pk Diff. Voltage at maximum amplitude setting (Amplitude code=11) with 100 Ohm differential termination Propagation Delay Time (Delay for data to travel from High-speed input to High-speed output) Skew between DOUT channels on a single crosspoint part Random Jitter at DOUT[0:67], the High Speed Electrical Data Port, specified as one sigma deviation of the 50% crossing point (RMS). Differential output measurement. Single channel input to single channel output. Deterministic Jitter at DOUT[0:67], the High Speed Electrical Data Port (pk-pk). Differential output measurement Single channel input to single channel output. Total jitter for 1E-12 BER (DJ + 14RJ). Differential output measurement. Single channel input to single channel output. Random Jitter at DOUT[0:67], the High Speed Electrical Data Port, specified as one sigma deviation of the 50% crossing point (RMS). Differential output measurement. Single channel input to all channels output. Units ps ps mV mV mV mV ns ps ps 2 0.25 200 550 800 1050 0.95 350 Min. Typ. 150 150 1600 Max.
DJ (Single)[3]
ps
30
TJ (Single)[3] RJ (Broadcast)[3]
ps ps
58 2.5
DJ (Broadcast)[3] Deterministic Jitter at DOUT[0:67], the High Speed Electrical Data Port (pk-pk). Differential output measurement. Single channel input to all channels output. TJ (Broadcast)[3] Drate Total jitter for 1E-12 BER (DJ + 14RJ). Differential output measurement. Single channel input to all channels output. Guaranteed Operating Rate
ps
40
ps Gbit/sec Note 2
75 3.2
Notes: 1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-. This measurement is made using a repeating 1010 pattern. Vop amplitude can be adjusted with the program register. 2. Minimum data rate depends on the value of AC input coupling capacitance and input resistance which is 100 Ohms between the positive and negative inputs. 3. Jitter measurement was carried out using a 3.3G BERT with a base jitter of 19ps for Deterministic Jitter and 0.97ps for Random Jitter. For eye diagrams, please see application notes. Jitter Measurement is taken using a K28.5 pattern at 3.2Gbaud data rate.
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Table 9. HDMP-3268 Thermal Characteristics[5] TA = 25C , VCC = VDD = VCC_DOUT = 2.5 V Symbol JT[2] JB[3] JC[4] JA[1] Parameter Thermal characterization parameter: Junction to case. Thermal characterization parameter: Junction to board. Thermal resistance: Junction to case Thermal resistance: Junction to ambient. Units
OC/W OC/W OC/W OC/W
Typ. 0.70 4.90 0.65 11.1
Note: Based on independent package testing done by Agilent. Refer to HDMP-3268 thermal management application note. 1. JA is based on thermal measurement in still air environment at 25C on a standard 5 x 5" FR4 PCB as specified in EIA/JESD 51-9. 2. JT is used to determine the actual junction temperature in a given application, using the following equation: TJ = JT x PD + TT , where TT is the measured temperature on top center of the package and PD is the power being dissipated. 3. JB is used to determine the actual junction temperature in a given application, using the following equation: TJ = JB x PD + TB, where TB is the measured board temperature along centerline at edge of the package and PD is the power being dissipated. 4. JC data is relevant for packages used with external heat sink. 5. Physical tests were carried out using 13.5 W as the power dissipation of the device.
Table 10. HDMP-3268 I/O Type Definitions I/O Type Definition HS_OUT HS_IN S CTL_IN CTL_I/O REFO REFI Differential high speed output, LV PECL compatible Differential high speed input, LV PECL compatible Power supply or ground Control logic input, LVTTL and SSTL_2 compatible Control logic input/output, LVTTL and SSTL_2 compatible Reference output voltage for LVTTL and SSTL_2 I/Os Reference input voltage for LVTTL and SSTL_2 I/Os
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Table 11. HDMP-3268 Pin Definitions Name DIN[0:67] Type HS_IN Signal High Speed Data Channel Inputs. Data channel inputs accepting 3.2 Gbit/sec data for rerouting to high speed outputs DOUT[0:67]+ and DOUT[0:67]-. Routing is controlled by the Address Registers.
DOUT[0:67] CNTL
HS_OUT High Speed Data Outputs. High-speed data channel outputs. Routing is controlled by the Address Registers. CTL_IN Control Input. Determines whether DATA[6:0] inputs are interpreted as addresses or control (input equalization and power off) settings. When CNTL is low the DATA[6:0] inputs are interpreted as addresses. When CNTL is high the DATA[6:0] inputs are interpreted as input equalization, amplitude, and power off settings. Data Inputs and Outputs. Address, input equalization, output amplitude and power off settings. Interpretation is determined by the state of the CNTL input. The direction of the data (input or output) is determined by the RW pin. DATA [6] is MSB. Channel Select. Selects one of the 68 control or address registers from which data is to be written or read. CH [6] is MSB. Chip Select. When CS is low the crosspoint switch chip is selected and the RW and DATA pins are enabled. This pin can be used to allow multiple crosspoint switches to operate on a shared bus. Read Write. This input is used to control whether address or program data is being written or read from the internal address and control registers. RW is 1 for Read mode and 0 for Write mode. Write Strobe. Input write strobe for writing DATA inputs to the internal address and control register. Data is latched into the internal registers on the rising edge of WSTB. Ground. Normally 0 volts. Logic Supply Voltage. Normally 2.5 volts. Switch Array Power Supply. Normally 2.5 volts. Used for internal PECL logic. It should be isolated from CMOS supply. High Speed Output Supply. Normally 2.5 volts. Used only for the last stage of the high-speed transmitter output cell. VCC_DOUT should be well bypassed to a ground plane. Termination. Set to high to terminate SSTL_2 I/O lines. Use. Selects address register bank to use to configure the switch. Set. Determines which address register is accessed by the CTL_I/O interface. LVTTL Voltage Reference Output. Nominally 1.4 V. Sets input threshold when logic inputs are connected to LVTTL signals Voltage Reference Input. Used with I-SSTL_2 inputs to the HDMP-3268. Voltage Reference Output. Used with O-SSTL_2 outputs from the HDMP-3268.
DATA[6:0]
CTL_I/O
CH[6:0] CS
CTL_IN CTL_IN
RW
CTL_IN
WSTB GND VDD VCC VCC_DOUT TERM USE SET VREF14 VREFI VREFO
CTL_IN S S S S CTL_IN CTL_IN CTL_IN REFO REFI REFO
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Table 12. HDMP-3268 Package Specifications 400 Ball 37.5 mm x 37.5 mm HPBGA Parameter Package Size Ball Matrix Ball Layout Ball Pitch Package Thickness mm mm Units mm mm Typ. 37.5x37.5 29x29 4 rows 1.27 2.93
Figure 9. HDMP-3268 pin locations. Note that the view is through the top of the package. If looking at the package bottom, ball A1 is at the upper right.
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Table 13. HDMP-3268 Detailed Pin Assignment
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 GND GND GND DOUT[58]GND DOUT[59]GND DOUT[62]GND DOUT[65]GND VREFI CH[2] CH[3] DATA[0] DATA[3] DATA[6] CNTL DOUT[0]+ GND DOUT[3]+ GND DOUT[6]+ GND DOUT[9]+ GND DOUT[12]+ GND GND GND VCC_DOUT DOUT[55]DOUT[58]+ DOUT[56]DOUT[59]+ DOUT[60]DOUT[62]+ DOUT[63]DOUT[65]+ DOUT[66]VREF14 CH[1] CH[6] DATA[1] DATA[4] WSTB SET DOUT[0]DOUT[2]+ DOUT[3]B22 B23 B24 B25 B26 B27 B28 B29 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 DOUT[5]+ DOUT[6]DOUT[8]+ DOUT[9]DOUT[11]+ DOUT[12]VCC_DOUT GND DIN[67]+ DIN[67]DOUT[55]+ DOUT[54]DOUT[56]+ DOUT[57]DOUT[60]+ DOUT[61]DOUT[63]+ DOUT[64]DOUT[66]+ DOUT[67]CH[0] CH[5] DATA[2] DATA[5] CS USE DOUT[1]+ DOUT[2]DOUT[4]+ DOUT[5]DOUT[7]+ DOUT[8]DOUT[10]+ DOUT[11]DOUT[13]+ DOUT[13]DIN[2]GND DIN[66]+ DIN[66]DOUT[54]+ VCC_DOUT DOUT[57]+ GND DOUT[61]+ GND DOUT[64]+ GND DOUT[67]+ VREFO D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 E1 E2 E3 E4 E26 E27 E28 E29 F1 F2 F3 F4 F26 F27 F28 F29 G1 G2 G3 G4 G26 G27 G28 G29 H1 H2 H3 H4 H26 H27 H28 H29 J1 J2 CH[4] VDD VDD RW TERM DOUT[1]GND DOUT[4]GND DOUT[7]GND DOUT[10]VCC_DOUT DIN[0]DIN[0]+ DIN[2]+ DIN[64]+ DIN[64]DIN[65]+ DIN[65]DIN[1]DIN[1]+ DIN[3]DIN[3]+ GND DIN[63]+ DIN[63]GND GND DIN[4]DIN[4]+ GND DIN[61]+ DIN[61]DIN[62]+ DIN[62]DIN[5]DIN[5]+ DIN[6]DIN[6]+ VCC DIN[60]+ DIN[60]GND GND DIN[7]DIN[7]+ VCC DIN[58]+ DIN[58]J3 J4 J26 J27 J28 J29 K1 K2 K3 K4 K26 K27 K28 K29 L1 L2 L3 L4 L26 L27 L28 L29 M1 M2 M3 M4 M26 M27 M28 M29 N1 N2 N3 N4 N26 N27 N28 N29 P1 P2 P3 P4 P26 P27 P28 P29 R1 R2 R3 R4 DIN[59]+ DIN[59]DIN[8]DIN[8]+ DIN[9]DIN[9]+ GND DIN[57]+ DIN[57]GND GND DIN[10]DIN[10]+ GND DIN[55]+ DIN[55]DIN[56]+ DIN[56]DIN[11]DIN[11]+ DIN[12]DIN[12]+ GND DIN[54]+ DIN[54]GND GND DIN[13]DIN[13]+ GND DIN[52]+ DIN[52]DIN[53]+ DIN[53]DIN[14]DIN[14]+ DIN[15]DIN[15]+ GND DIN[51]+ DIN[51]GND VCC DIN[16]DIN[16]+ GND DIN[50]DIN[50]+ DIN[49]+ DIN[49]-
15
Table 13. HDMP-3268 Detailed Pin Assignment (continued)
R26 R27 R28 R29 T1 T2 T3 T4 T26 T27 T28 T29 U1 U2 U3 U4 U26 U27 U28 U29 V1 V2 V3 V4 V26 V27 V28 V29 W1 W2 W3 W4 W26 W27 W28 W29 Y1 Y2 Y3 Y4 Y26 Y27 Y28 Y29 AA1 AA2 AA3 AA4 AA26 AA27 DIN[18]DIN[18]+ DIN[17]+ DIN[17]GND DIN[48]DIN[48]+ VCC GND DIN[19]+ DIN[19]GND DIN[47]DIN[47]+ DIN[46]DIN[46]+ DIN[21]+ DIN[21]DIN[20]+ DIN[20]GND DIN[45]DIN[45]+ GND GND DIN[22]+ DIN[22]GND DIN[44]DIN[44]+ DIN[43]DIN[43]+ DIN[24]+ DIN[24]DIN[23]+ DIN[23]GND DIN[42]DIN[42]+ GND GND DIN[25]+ DIN[25]VCC DIN[41]DIN[41]+ DIN[40]DIN[40]+ DIN[27]+ DIN[27]AA28 AA29 AB1 AB2 AB3 AB4 AB26 AB27 AB28 AB29 AC1 AC2 AC3 AC4 AC26 AC27 AC28 AC29 AD1 AD2 AD3 AD4 AD26 AD27 AD28 AD29 AE1 AE2 AE3 AE4 AE26 AE27 AE28 AE29 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 DIN[26]+ DIN[26]VCC DIN[39]DIN[39]+ GND GND DIN[28]+ DIN[28]VCC DIN[38]DIN[38]+ DIN[37]DIN[37]+ DIN[30]+ DIN[30]DIN[29]+ DIN[29]GND DIN[36]DIN[36]+ GND GND DIN[31]+ DIN[31]GND DIN[35]DIN[35]+ DIN[34]DIN[34]+ DIN[33]+ DIN[33]DIN[32]+ DIN[32]GND DOUT[53]+ DOUT[53]GND DOUT[50]+ GND DOUT[47]+ GND DOUT[44]+ GND DOUT[40]+ GND DOUT[37]+ VCC_DOUT DOUT[33]+ GND AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 DOUT[30]GND DOUT[27]GND DOUT[23]GND DOUT[20]GND DOUT[17]GND DOUT[14]+ DOUT[14]GND DOUT[52]+ DOUT[52]GND DOUT[49]+ DOUT[50]DOUT[46]+ DOUT[47]DOUT[43]+ DOUT[44]DOUT[41]+ DOUT[40]DOUT[38]+ DOUT[37]DOUT[35]+ DOUT[33]DOUT[32]DOUT[30]+ DOUT[29]DOUT[27]+ DOUT[26]DOUT[23]+ DOUT[24]DOUT[20]+ DOUT[21]DOUT[17]+ DOUT[18]GND DOUT[15]+ DOUT[15]GND GND DOUT[51]+ DOUT[49]DOUT[48]+ DOUT[46]DOUT[45]+ DOUT[43]AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 DOUT[42]+ DOUT[41]DOUT[39]+ DOUT[38]DOUT[36]+ DOUT[35]DOUT[34]DOUT[32]+ DOUT[31]DOUT[29]+ DOUT[28]DOUT[26]+ DOUT[25]DOUT[24]+ DOUT[22]DOUT[21]+ DOUT[19]DOUT[18]+ DOUT[16]GND GND GND GND DOUT[51]GND DOUT[48]GND DOUT[45]VCC_DOUT DOUT[42]GND DOUT[39]GND DOUT[36]GND DOUT[34]+ GND DOUT[31]+ GND DOUT[28]+ GND DOUT[25]+ VCC_DOUT DOUT[22]+ GND DOUT[19]+ GND DOUT[16]+ GND GND
16
Package Dimensions
aaa (4x) A B
A1 BALL CORNER
D
STANDARD EDGE (ROUTED)
P
6
Agilent
HDMP-3268
7 E2
2d ccc A-A SECTION VIEW A A2 bbb C C A1 SIDE VIEW SEATING PLANE 3 0.30 M C A B 0.10 M C D1,M b 5 M1
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ
LLLLLLL-NN G YYWW RE.FG COUNTRY OF ORIGIN
E
A3
ddd c D2 TOP VIEW ELECTRICALLY 7 ISOLATED HEATSPREADER
A1 BALL CORNER
BODY SIZE SYMBOL A A1 MIN. 2.63 0.50 2.13 1.63 - 35.46 36.00 - 35.46 36.00
37.5 mm x 37.5 mm NOM. 2.93 0.60 2.33 1.82 37.50 35.56 36.50 37.50 35.56 36.50 29 x 29 3-6 0.60 0.75 - 1.27 - - - - - - - - - 0.20 0.25 0.20 0.20 - 0.90 - MAX. 3.23 0.70 2.53 2.03 - 35.66 37.00 - 35.66 37.00
A
A
A2 A3 E1,N D D1 D2 7 E E1 E2 7 M,N M1 5 b d e 2
B e
e 7 4 B BOTTOM VIEW DIE SIDE
0.50
NOTES: UNLESS OTHERWISE SPECIFIED aaa 1 2 ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994. DIMENSION "d" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. SHAPE AT CORNER. SINGLE FORM bbb ccc ddd 3 P 6
0.20
4 5 6
NUMBER OF ROWS IN FROM EDGE TO CENTER. SEATING PLANE CLEARANCE: MINIMUM HEIGHT OF ENCAPSULANT ABOVE SEATING PLANE. D2 AND E2 SPECIFY THE STANDARD ELECTRICALLY ISOLATED HEATSPREADER SIZE. SEE HEATSPREADER OPTIONS SHEET 1 FOR OPTIMAL SIZES.
7
17
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright (c) 2002 Agilent Technologies, Inc. September 26, 2002 5988-7129EN

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